1. Field of the Invention
The present invention relates to a driving circuit of a plasma display panel (PDP), and more particularly, to a driving circuit of a PDP in which high resolution of pixels of 640xc3x97480 or more can be realized by minimizing loading time of a digital picture signal in a driving method of a flat panel display.
2. Discussion of the Related Art
Generally, a PDP is discharged by adjusting a voltage applied between vertical and horizontal electrodes of a cell constituting pixels. The amount of discharged light is adjusted by varying discharge time in the cell.
The overall screen of the PDP is formed in such a manner that the PDP is driven in a matrix arrangement by applying a write pulse for inputting a digital picture signal to the vertical and horizontal electrodes in each cell, a scan pulse for scanning, a sustain pulse for sustaining discharge, and an erase pulse for erasing discharge of the discharged cell.
Grey level required for picture display is realized by making discharge time of each cell be difference within a given time period (for example, {fraction (1/30)} second in NTSC TV signal) required for the overall picture display. At this time, brightness of the screen is determined by grey level from when each of the cell is driven at a maximum level. To increase the brightness, the driving circuit should be designed in such a manner that discharge time of the cell is sustained as long as possible within a given time period for displaying one screen.
FIG. 1 is a block diagram illustrating a driving circuit of a conventional PDP.
As shown in FIG. 1, the PDP includes a panel 1, an address electrode driver 4, a scan driver 3, a common electrode driver 5, and a controller 2. The panel 1 is formed by vacuum coupling of a front glass substrate and a rear glass substrate. On the front glass substrate, a scan electrode and a common electrode are formed. On the rear glass substrate, an address electrode is formed. The address electrode driver 4 applies digital picture data to the address electrode. The scan driver 3 applies scan data to the panel 1 to determine whether or not the panel 1 should be driven. The common electrode driver 5 drives the common electrode of the panel 1. The controller 2 provides various signals and data required for driving the drivers 3, 4 and 5.
In the conventional PDP, externally applied various signals such as clock signals, RGB signals, vertical synchronizing signals Vsync, and horizontal synchronizing signals Hsync are provided to the controller 2. The controller 2 applies scan data and control signals to the scan driver 3 and address data and an address clock to the address electrode driver 4.
If the scan electrode and the common electrode are driven in response to the signals applied to the respective drivers, the data provided to the address electrode can be displayed on the panel 1.
The scan driver 3 is a very important factor, which determines whether or not the panel 1 should be driven. The detailed configuration of the scan driver 3 will be described with reference to FIG. 2.
As shown in FIG. 2, the scan driver 3 includes a shift register 12, a latch part 13, and a high voltage pulse generator 14. The shift register 12 transfers scan data per 1 bit to each electrode line in parallel in response to predetermined clock pulse. The latch part 13 counts the scan data of the shift register 12. The high voltage pulse generator 14 outputs the scan data output from the latch part 13 by loading the scan data to an alternating current (AC) high voltage pulse.
The high voltage pulse generator 14 can randomly vary the outputs of the scan data in response to a polarity signal pol and a selection signal cs. However, since the shift register 12 shifts total m bit scan data per 1 bit in response to clock pulse of 25 MHz, the time required for loading of the scan data is 1.28 xcexcs per 32 bit and 1.6 xcexcs per 40 bit.
The conventional PDP has a problem. That is to say, for loading of the scan data at a desired bit, the scan driver requires a predetermined sized shift register. To randomly vary the final output data of the high voltage pulse generator, shift clock is required as much as the size of the shift register. This results in that the loading time of 1 xcexcs or more is required for loading of the scan data to the shift register.
Accordingly, the present invention is directed to a driving circuit of a PDP that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a driving circuit of a PDP in which loading time for loading scan data to each electrode line can be minimized and final output data of a high voltage pulse generator can randomly be varied.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice or the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a decoder between an output terminal of a conventional shift register and an input terminal of a latch part. Alternatively, instead of the shift register, there are provided a decoder and a line selector between an input terminal of n bit scan data and an input terminal of a latch part. Therefore, the n bit scan data can be decoded to desired electrode lines. As a result, a driving circuit of an AC PDP can be designed, in which loading time of the scan data is 1 xcexcs or below.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.